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 PD - 9.1525
IRF9Z34NS/L
HEXFET(R) Power MOSFET
Advanced Process Technology Surface Mount (IRF9Z34NS) l Low-profile through-hole (IRF9Z34NL) l 175C Operating Temperature l Fast Switching l P-Channel l Fully Avalanche Rated Description
l l
D
VDSS = -55V RDS(on) = 0.10
G
ID = -19A
S
Fifth Generation HEXFETs from International Rectifier utilize advanced processing techniques to achieve extremely low on-resistance per silicon area. This benefit, combined with the fast switching speed and ruggedized device design that HEXFET Power MOSFETs are well known for, provides the designer with an extremely efficient and reliable device for use in a wide variety of applications. The D2Pak is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible onresistance in any existing surface mount package. The D2 Pak is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2.0W in a typical surface mount application. The through-hole version (IRF9Z34NL) is available for lowprofile applications.
D 2 Pak
T O -2 6 2
Absolute Maximum Ratings
Parameter
ID @ TC = 25C ID @ TC = 100C IDM PD @TA = 25C PD @TC = 25C VGS EAS IAR EAR dv/dt TJ TSTG Continuous Drain Current, V GS @ -10V Continuous Drain Current, V GS @ -10V Pulsed Drain Current Power Dissipation Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
Max.
-19 -14 -68 3.8 68 0.45 20 180 -10 6.8 -5.0 -55 to + 175 300 (1.6mm from case )
Units
A W W W/C V mJ A mJ V/ns C
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient ( PCB Mounted,steady-state)**
Typ.
--- ---
Max.
2.2 40
Units
C/W
8/25/97
IRF9Z34NS/L
Electrical Characteristics @ TJ = 25C (unless otherwise specified)
V(BR)DSS
V(BR)DSS/TJ
RDS(on) VGS(th) gfs IDSS I GSS Qg Qgs Qgd td(on) tr t d(off) tf LS Ciss Coss Crss
Parameter Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Forward Transconductance Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Source Inductance Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. -55 --- --- -2.0 4.2 --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Typ. --- -0.05 --- --- --- --- --- --- --- --- --- --- 13 55 30 41 7.5 620 280 140
Max. Units Conditions --- V VGS = 0V, ID = -250A --- V/C Reference to 25C, ID = -1mA 0.10 VGS = -10V, I D = -10A -4.0 V VDS = VGS , ID = -250A --- S V DS = -25V, I D = -10A -25 VDS = -55V, VGS = 0V A -250 VDS = -44V, VGS = 0V, TJ = 150C 100 V GS = 20V nA -100 VGS = -20V 35 I D = -10A 7.9 nC VDS = -44V 16 VGS = -10V, See Fig. 6 and 13 --- VDD = -28V --- I D = -10A ns --- R G = 13 --- RD = 2.6, See Fig. 10 Between lead, nH --- and center of die contact --- VGS = 0V --- pF VDS = -25V --- = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
V SD t rr Q rr t on Notes:
Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min. Typ. Max. Units
Conditions D MOSFET symbol --- --- -19 showing the A G integral reverse --- --- -68 p-n junction diode. S --- --- -1.6 V TJ = 25C, IS = -10A, VGS = 0V --- 54 82 ns TJ = 25C, IF = -10A --- 110 160 nC di/dt = -100A/s Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Pulse width 300s; duty cycle 2%.
Uses IRF9Z34N data and test conditions
Starting TJ = 25C, L = 3.6mH
RG = 25, I AS = -10A. (See Figure 12)
TJ 175C ** When mounted on 1" square PCB (FR-4 or G-10 Material ). For recommended footprint and soldering techniques refer to application note #AN-994.
I SD -10A, di/dt -290A/s, VDD V(BR)DSS ,
IRF9Z34NS/L
100
VGS - 15V - 10V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTT OM - 4. 5V TOP
100
-ID , D ra in -to -S o u rc e C u rre n t (A )
10
-ID , D ra in -to -S o u rc e C u rre n t (A )
VGS - 15V - 10V - 8.0V - 7.0V - 6.0V - 5.5V - 5.0V BOTT OM - 4. 5V TOP
10
-4 .5V 20 s PU LSE W ID TH TJ 1 75C TC = 175C
0.1 1 10
-4 .5V
1 0.1 1
2 0 s PU LS E W ID TH T = 2 5C T cJ = 25C A
10 100
1
100
A
-VD S , Drain-to-Source Voltage (V)
-VD S , Drain-to-Source V oltage (V )
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
2.0
R D S (o n ) , D ra in -to -S o u rc e O n R e si sta n ce (N o rm a li ze d )
I D = -17 A
-I D , D rain -to- S our ce C urr ent ( A )
1.5
T J = 2 5 C T J = 1 7 5 C
10
1.0
0.5
1 4 5 6 7
V DS = -2 5 V 2 0 s P U L S E W ID T H
8 9 10
A
0.0 -60 -40 -20 0 20 40 60 80
VG S = -10 V
100 120 140 160 180
A
-VG S , Ga te-to-S o urce V oltage (V )
T J , Junction T emperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance Vs. Temperature
IRF9Z34NS/L
1200
-V G S , G a te -to -S o u rc e V o lta g e (V )
1000
V GS C is s C rs s C os s
= = = =
0V , f = 1MH z C gs + C g d , Cds SH OR TED Cgd C ds + C gd
20
I D = -10 A V DS = -44 V V DS = -28 V
16
C , C a p a c ita n c e (p F )
800
C i ss C os s
12
600
8
400
C rs s
200
4
0 1 10 100
A
0 0 10 20
FO R TEST C IR C U IT SEE F IGU R E 1 3
30 40
A
-VD S , Drain-to-Source V oltage (V)
Q G , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
-IS D , R e ve rse D ra in C u rre n t (A )
OPE R ATIO N IN TH IS A RE A LIMITE D BY R D S(o n)
10
-I D , D ra in C u rre n t (A )
100 1 0s
T J = 1 75 C T J = 25 C
100 s 10 1m s
1
T C = 5C TC = 225C
0.1 0.2 0.4 0.6 0.8 1.0 1.2
VG S = 0 V
1.4
A
1 1
T J = 1 75C Sin gle Pu lse
10
10m s
1.6
A
100
-VS D , S ource-to-Drain V oltage (V )
-VD S , Drain-to-Source V oltage (V )
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
IRF9Z34NS/L
20
VDS VGS
RD
D.U.T.
+
I D , Drain Current (A)
15
-10V
10
Pulse Width 1 s Duty Factor 0.1 %
Fig 10a. Switching Time Test Circuit
5
td(on) tr t d(off) tf
VGS 10%
0 25 50 75 100 125 150 175
T C , Case Temperature
( C)
90% VDS
Fig 9. Maximum Drain Current Vs. Case Temperature
Fig 10b. Switching Time Waveforms
10
Thermal Response (Z thJC )
1
D = 0.50 0.20 0.10 0.05 PDM SINGLE PULSE (THERMAL RESPONSE) t1 t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.0001 0.001 0.01 0.1
0.1
0.02 0.01
0.01 0.00001
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
-
RG
VDD
IRF9Z34NS/L
VDS
E A S , S in g le P u ls e A va la n c h e E n e rg y (m J)
L
500
TOP
400
RG -2 0V tp
D .U .T IA S 0.0 1 D R IV E R
VDD A
BO TTOM
ID -4 .2A -7.2 A -10 A
300
200
15V
Fig 12a. Unclamped Inductive Test Circuit
100
0 25 50 75 100 125 150
A
175
I AS
Starting TJ , Junction T emperature (C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
tp V(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
-10V
QGS VG QGD
VGS
-3mA
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
+
D.U.T.
-
VDS
IRF9Z34NS/L
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T* Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
+
-
+
RG VGS * dv/dt controlled by RG * I SD controlled by Duty Factor "D" * D.U.T. - Device Under Test
+ VDD
*
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive P.W. Period D=
P.W. Period
[VGS=10V ] ***
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
[ VDD]
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
[ ISD]
*** VGS = 5.0V for Logic Level and 3V Drive Devices Fig 14. For P-Channel HEXFETS
IRF9Z34NS/L
D2Pak Package Outline
10.54 ( .415) 10.29 ( .405) 1.40 (.055) MAX. -A2
4.69 (.185) 4.20 (.165)
-B 1.32 (.052) 1.22 (.048)
10.16 (.400) RE F .
6.47 (.255) 6.18 (.243) 15.49 (.610) 14.73 (.580) 5.28 (.208) 4.78 (.188) 2.79 (.110) 2.29 (.090) 2.61 (.103) 2.32 (.091) 8.89 (.350) RE F.
1.78 (.070) 1.27 (.050)
1
3
3X
1.40 (.055) 1.14 (.045) 5.08 ( .200)
0.93 (.037) 3X 0.69 (.027) 0.25 (.010) M BAM
0.55 (.022) 0.46 (.018)
1.39 (.055) 1.14 (.045)
MINIMUM RECO MM ENDED F OO TP RINT 11.43 (.450)
NO TE S: 1 DIM ENS IO NS AF T ER S OLDE R DIP . 2 DIM ENS IO NING & TO LERA NCING PE R ANS I Y 14.5M, 1982. 3 CO NT RO LLING DIME NSIO N : INCH. 4 HE AT SINK & LEAD DIMEN SION S DO NO T INCLUDE BURRS.
LE AD ASS IG NM ENT S 1 - G AT E 2 - DRA IN 3 - S OU RC E
8.89 (.350) 17.78 (.700)
3.81 (.150) 2.08 (.082) 2X 2.54 (.100) 2X
Part Marking Information
D2Pak
IN TER NATION AL REC TIFIER L OGO AS SEMBLY LOT CODE
A
PART NU MBER F53 0S 9246 9B 1M
DATE CODE (YYW W ) YY = YEAR W W = W EE K
IRF9Z34NS/L
Package Outline
TO-262 Outline
Part Marking Information
TO-262
IRF9Z34NS/L
Tape & Reel Information
D2Pak
TR R
1 .6 0 (.0 6 3 ) 1 .5 0 (.0 5 9 ) 4 .1 0 (.1 6 1) 3 .9 0 (.1 5 3) 1 .6 0 (.0 6 3) 1 .5 0 (.0 5 9) 0 .3 68 (.0 14 5 ) 0 .3 42 (.0 13 5 )
F E E D D IR E C TIO N 1 .8 5 (.0 7 3 )
1 .6 5 (.0 6 5 )
11 .6 0 (. 45 7 ) 11 .4 0 (. 44 9 )
15 .4 2 (.60 9 ) 15 .2 2 (.60 1 )
2 4 .30 (.9 5 7) 2 3 .90 (.9 4 1)
TR L
1 0. 90 (.4 29 ) 1 0. 70 (.4 21 ) 1. 75 (.0 69 ) 1. 25 (.0 49 ) 1 6. 10 (.6 34 ) 1 5. 90 (.6 26 ) 4 .7 2 (.1 3 6) 4 .5 2 (.1 7 8)
FE E D D IR E C TIO N
1 3.5 0 (. 532 ) 1 2.8 0 (. 504 )
2 7.4 0 (1 .079 ) 2 3.9 0 (.9 41) 4
33 0.0 0 (14. 17 3) M AX .
6 0.0 0 (2 .36 2) M IN .
N O T ES : 1. C O M F O R M S T O EIA -418 . 2. C O N T R O LLIN G D IM EN SIO N : M ILLIM E T ER . 3. D IM E N S IO N M EA S U R E D @ H U B . 4. IN C LU D E S F L AN G E D IS T O R T IO N @ O U T E R ED G E.
26 .40 (1. 03 9) 24 .40 (.9 61 ) 3
3 0.4 0 (1 .19 7) MA X . 4
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